32-bit Pipelined RISC-V CPU
A RISC-V (RV32I) processor designed gate-by-gate in Logisim Evolution, with a pipelined datapath, forwarding, and hazard handling.
Overview
For a computer architecture course project, I built a working 32-bit CPU at the digital logic level — every component from the ALU up to the control unit designed as circuits in Logisim Evolution. The processor executes a substantial subset of the RISC-V RV32I integer instruction set on a two-stage pipeline and passes an automated test suite of assembly programs.
Architecture / Approach
- Pipelined datapath: a two-stage design — an Instruction Fetch / Decode stage that fetches from instruction memory and reads the register file, and an Execute / Memory / Writeback stage that performs the ALU operation, accesses data memory, and writes results back.
- Hazard handling: values computed in the second stage are forwarded back to the first stage so dependent instructions don't stall, and taken branches and jumps flush the pipeline to keep control flow correct.
- Custom components: the ALU, a 32×32-bit register file, the immediate generator (sign extension for every RISC-V instruction format), a branch comparator, the main control logic, and partial load/store units that handle byte and halfword memory access with correct masking and sign extension.
- Instruction support: arithmetic and logic ops and their immediate variants (add, sub, xor, shifts, comparisons), byte/halfword/word loads and stores, all six conditional branches, jal/jalr, and lui/auipc.
- Testing: each component has its own test harness, and full programs are assembled with the Venus RISC-V assembler/simulator to generate reference outputs that the circuit is automatically checked against.
Results / What I learned
The finished CPU runs real RISC-V assembly programs — including unit tests for every component and integration tests covering immediates, memory operations, branches, and jumps — and passes the full automated suite. Building the datapath wire-by-wire made concepts like forwarding, pipeline flushes, and instruction decoding concrete in a way that reading about them never could.